Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Narasimhulu Thoti, Yiming Li*, Sekhar Reddy Kola

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages82-83
Number of pages2
ISBN (Electronic)9781728142326
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

Fingerprint Dive into the research topics of 'Scaling Limitations of Line TFETs at Sub-8-nm Technology Node'. Together they form a unique fingerprint.

Cite this