Scaling limit of silicon nitride gate dielectric for future CMOS technologies

Yee Chia Yeo*, Qiang Lu, Wen Chin Lee, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

The direct tunneling gate currents through Si3N4 in both N- and P-MOSFETs were examined using an analytical model. Excellent agreement was observed between model and experimental data.

Original languageEnglish
Pages65-66
Number of pages2
DOIs
StatePublished - 1 Jan 2000
Event58th Device Research Conference (58th DRC) - Denver, CO, USA
Duration: 19 Jun 200021 Jun 2000

Conference

Conference58th Device Research Conference (58th DRC)
CityDenver, CO, USA
Period19/06/0021/06/00

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