Scalable VLSI architectures for full-search block matching algorithms

Yuan Hau Yeh*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

5 Scopus citations

Abstract

This paper presents two VLSI architectures for full search block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by PE for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save I/O pin-count.

Original languageEnglish
Pages1035-1038
Number of pages4
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3) - Lausanne, Switz
Duration: 16 Sep 199619 Sep 1996

Conference

ConferenceProceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3)
CityLausanne, Switz
Period16/09/9619/09/96

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