This paper presents two VLSI architectures for full search block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by PE for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save I/O pin-count.
|Number of pages||4|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3) - Lausanne, Switz|
Duration: 16 Sep 1996 → 19 Sep 1996
|Conference||Proceedings of the 1996 IEEE International Conference on Image Processing, ICIP'96. Part 2 (of 3)|
|Period||16/09/96 → 19/09/96|