@inproceedings{2e96aa1bd4d14b79ad9181fc60284dc5,
title = "SBD layout optimization with effect of N-well to p-substrate pn junctions in 0.18 μm CMOS process",
abstract = "The effect of layout on silicon SBD in CMOS process is studied in this paper. The size of anode area not only affects the series resistance and SBD junction capacitance but also causes serious parasitic effect from cathode to the p-substrate. Typically, an SBD of a small unit anode has a better cut-off frequency than that of a large unit anode. The cutoff frequency of a small anode Schottky diode is about 700 GHz in a standard 0.18 μm CMOS process. However, a SBD with a small unit anode is prone to the effect of p-substrate to N-well pn junction capacitor. This paper has characterized SBDs of different anode sizes with bottom and side-wall effect of p-substrate to N-well to select an optimal unit-anode area by reducing the substrate effect and providing sufficient fT for high frequency applications.",
keywords = "CMOS, Cutoff frequency, Millimeter-wave, N-well, Pn junction, Schottky barrier diode",
author = "Chang, {Wei Ling} and Chinchun Meng and Huang, {Guo Wei}",
year = "2017",
month = may,
day = "17",
doi = "10.1109/APMC.2016.7931323",
language = "English",
series = "Asia-Pacific Microwave Conference Proceedings, APMC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 Asia-Pacific Microwave Conference, APMC 2016 - Proceedings",
note = "null ; Conference date: 05-12-2016 Through 09-12-2016",
}