Impact of threshold voltage (Vt) level from the cells at neighboring word-lines (WLs) on random telegraph noise (RTN) in floating-gate (FG) NAND flash memory is investigated. Due to aggressive pitch scaling, two-step programming is utilized to suppress the cell-to-cell interference and to achieve multi-level-cell (MLC) operation [1,2]. Such scheme could compromise the interference to get optimized Vt distributions at selected WL (sel-WL) even if the cells at the adjacent WLs reveal various Vt states. Once the neighboring WL keeps at low-Vt state, a compact RTN distribution is obtained. TCAD device simulation putting different stored charges to modulate the adjacent equivalent pass gate voltage (equi-Vpass), further confirms that RTN variation strongly correlates to the conduction current path beneath the sel-WLs. The reduction of RTN influence by increasing the equi-Vpass is then demonstrated. Finally, the optimal source/drain dosage range would be determined.