Response speed of negative capacitance FinFETs

Daewoong Kwon, Yu Hung Liao, Yen Kai Lin, Juan Pablo Duarte, Korok Chatterjee, Ava J. Tan, Ajay K. Yadav, Chen-Ming Hu, Zoran Krivokapic, Sayeef Salahuddin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations


We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested-per-stage delay as small as 7.2 ps.

Original languageEnglish
Title of host publication2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781538642160
StatePublished - 25 Oct 2018
Event38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States
Duration: 18 Jun 201822 Jun 2018

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


Conference38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
CountryUnited States

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