Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process

Chih Ting Yeh, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45μm can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25°C under the normal circuit operating condition with 1V bias.

Original languageEnglish
Title of host publication2013 IEEE International Reliability Physics Symposium, IRPS 2013
DOIs
StatePublished - 7 Aug 2013
Event2013 IEEE International Reliability Physics Symposium, IRPS 2013 - Monterey, CA, United States
Duration: 14 Apr 201318 Apr 2013

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2013 IEEE International Reliability Physics Symposium, IRPS 2013
CountryUnited States
CityMonterey, CA
Period14/04/1318/04/13

Keywords

  • Electrostatic discharge (ESD)
  • gate leakage
  • power-rail ESD clamp circuit
  • silicon-controlled rectifier (SCR)

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    Yeh, C. T., & Ker, M-D. (2013). Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process. In 2013 IEEE International Reliability Physics Symposium, IRPS 2013 [6532071] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2013.6532071