Resistive Approach for Extraction of Bias-Dependent Parasitic Resistance, Mobility and Virtual Gate Length in GaN HEMT

Pragyey Kumar Kaushik*, Sankalp Kumar Singh, Ankur Gupta, Ananjan Basu, Edward Yi Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we introduce a resistive approach to extract various device performance parameters such as contact resistance, mobility and effective gate length. Without passivation of the un-gated region, HEMT device leads to forming of an extra gate length either side of gate called virtual gate length (dLG). Carrier mobility (µC) of 2DEG and dLG also depends upon VGS (gate bias). The depleted channel also reduces the device current causing a significant increase in source/drain resistance (RS/RD).

Original languageEnglish
Title of host publication2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-118
Number of pages2
ISBN (Electronic)9781728197357
DOIs
StatePublished - Jun 2020
Event2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
Duration: 13 Jun 202014 Jun 2020

Publication series

Name2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
CountryUnited States
CityHonolulu
Period13/06/2014/06/20

Keywords

  • high electron mobility transistor
  • parameter extraction
  • two-dimensional electron gas
  • Virtual gate

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