Research of electroplating and electroless plating for low temperature bonding in 3D heterogeneous integration

Yu Chen Hu, Yao Jen Chang, Chun Shen Wu, Yung Mao Cheng, Wei Jen Chen, Kuan Neng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 μm bump pitch, 40 μm diameter of Cu/Sn μ-bump and 50 μm diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.

Original languageEnglish
Title of host publication2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference
Subtitle of host publicationChallenges of Change - Shaping the Future, IMPACT 2014 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages290-293
Number of pages4
ISBN (Electronic)9781479977277
DOIs
StatePublished - 1 Jan 2014
Event9th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2014 - Taipei, Taiwan
Duration: 22 Oct 201424 Oct 2014

Publication series

Name2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference: Challenges of Change - Shaping the Future, IMPACT 2014 - Proceedings

Conference

Conference9th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2014
CountryTaiwan
CityTaipei
Period22/10/1424/10/14

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