Reliability test guidelines for a 0.18 μm generation multi-oxide CMOS technology for system-on-chip applications

Shang Jr Chen*, Ching Chung Lin, Steve S. Chung, Jung Chun Lin, Chih Hsiun Chu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


With an increase of power dissipation and integrated-circuit (IC) density in system-on-a-Chip (SoC), it is not sufficient to determine complementary metal-oxide-semiconductor (CMOS) device lifetime by merely monitoring stress-bias conditions, such as hot-carrier (HC) stress. The temperature effect is a significant factor affecting the device lifetime. More and more evidence has been reported which indicates the significance of the temperature effect on device reliability, particularly the negative bias and temperature instability (NBTI) in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs). In this work, a complete test of seven kinds of stress conditions which affect device lifetime will be carried out for 0.18 μm generation SoC technology CMOS devices with multiple oxide thicknesses and multiple applied biases. Based on these results, we provide guidelines for next-generation SoC CMOS technology. In nMOSFETs, the temperature effect is weak and therefore conventional hot carrier (HC) stress (i.e., maximum substrate current stress, IBmax) at room temperature dominates the device lifetime. However, in pMOSFETs, the temperature effect is critically important for determining the device lifetime. It was found that NBTI-like HC stress (VG = VD at high-T) has been shown to dominate the device lifetime for both 0.18 μm and 0.35 μm pMOSFETs. Furthermore, the NBTI effect will become more pronounced with the device channel length scaling.

Original languageEnglish
Pages (from-to)1928-1932
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number4 B
StatePublished - 1 Apr 2003


  • Device lifetime
  • Multi-oxide technology
  • Negative bias temperature instability
  • Reliability issue
  • System-on-a-chip
  • Temperature effect

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