In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with HfO 2 gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the HfO 2 gate dielectric is observed for the PBS and PBTI of the HfO 2 LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the HfO 2 LTPS-TFT.
- HfO gate dielectric
- Hot-carrier stress (HCS)
- Low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT)
- Negative-bias temperature instability (NBTI)
- Positive-bias temperature instability (PBTI)