Reliability-aware design automation flow for analog circuits

Chien-Nan Liu, Yen Lung Chen, Tsung Yu Liu, Tai Chen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Manually designing analog circuits is often considered as a difficult task that takes a lot of time. If a design automation environment is available for analog circuits, it is useful for designers to cope with the increasing challenges in advance process. In this paper, a reliability-aware circuit sizing technique is proposed to consider process variation, circuit aging, and layout-dependent effects simultaneously. A reliability-aware analog layout automation technique is also proposed to consider both placement and routing while improving the reliability of the generated layout. These reliability-aware design automation techniques have been integrated to build a complete synthesis environment from specifications to layout. As shown in the experimental results, the proposed automation flow does help designers solve the reliability issues efficiently.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 8 Feb 2016
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2 Nov 20155 Nov 2015

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Conference

Conference12th International SoC Design Conference, ISOCC 2015
CountryKorea, Republic of
CityGyeongju
Period2/11/155/11/15

Keywords

  • analog design automation
  • circuit reliability

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