In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n + region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n + region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n + region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n + region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of V G is less than half of V D .
- Hot-carrier (HC) stress
- polycrystalline silicon thin-film transistors (poly-Si TFTs)
- positive gate bias (PGB) stress
- self-heating (SH) stress
- symmetric S/D
- vertical channel