Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond

Ming H. Yu, J. H. Li, H. H. Lin, C. H. Chen, K. C. Ku, C. F. Nieh, H. Hisa, Y. M. Sheu, C. W. Tsai, Y. L. Wang, H. Y. Chu, Huang-Chung Cheng, T. L. Lee, S. C. Chen, M. S. Liang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations


The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.

Original languageEnglish
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
StatePublished - 1 Dec 2006
Event2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States
Duration: 10 Dec 200613 Dec 2006

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918


Conference2006 International Electron Devices Meeting, IEDM
CountryUnited States
CitySan Francisco, CA

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