Register renaming for x86 superscalar design

Chang Chung Liu*, R. Ming Shiu, Chung-Ping Chung

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Register renaming eliminates storage conflicts for registers to allow more instruction level parallelism. This idea requires nontrivial implementation, however, especially when registers are accessible with different fields and data lengths. As a result, not all bits in a register are to be updated upon a register write, and a register read may data-dependent on multiple register writes. We propose two hardware renaming schemes to solve these difficulties: One for its ultimate performance, and the other for its desirable cost/performance ratio. We evaluate these two schemes on an aggressive superscalar machine model for Intel 80x86 architecture. Simulation results show that the second scheme can effectively reduce the hardware cost while retaining about 99% of the performance of the first.

Original languageEnglish
Pages336-343
Number of pages8
StatePublished - 1 Jan 1996
EventProceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS'96) - Tokyo, Jpn
Duration: 3 Jun 19966 Jun 1996

Conference

ConferenceProceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS'96)
CityTokyo, Jpn
Period3/06/966/06/96

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