Reed-Solomon product-code (RS-PC) decoder for DVD applications

Hsie-Chia Chang; C. Shung

doi:10.1109/ISSCC.1998.672548

Reed-Solomon product-code (RS-PC) decoder for DVD applications

Hsie-Chia Chang^*, C. Shung

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

A Reed-Solomon product-code (RS-PC) is used in digital versatile disk (DVD) for error correction to mitigate the errors introduced during manufacturing or by user damage. The RS-PC decoder chip contains two frame buffer controllers that interface with two off-chip frame buffers, a row RS decoder and a column RS decoder. The parallel architecture minimizes the amount of frame buffer access and timing constraints on the RS decoders. Each RS decoder contains a syndrome calculator, a key equation solver, a Chien search and an error value evaluator. The 4.22×64 mm² chip with a 2.90×2.88 mm² core uses a cell library in a 0.6 μm SPDM CMOS process.

Original language	English
Pages (from-to)	390-391, 470
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs	https://doi.org/10.1109/ISSCC.1998.672548
State	Published - 1 Jan 1998
Event	Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA Duration: 5 Feb 1998 → 7 Feb 1998

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@article{6e84fb7b9d5545baa39c507a539e6475,

title = "Reed-Solomon product-code (RS-PC) decoder for DVD applications",

abstract = "A Reed-Solomon product-code (RS-PC) is used in digital versatile disk (DVD) for error correction to mitigate the errors introduced during manufacturing or by user damage. The RS-PC decoder chip contains two frame buffer controllers that interface with two off-chip frame buffers, a row RS decoder and a column RS decoder. The parallel architecture minimizes the amount of frame buffer access and timing constraints on the RS decoders. Each RS decoder contains a syndrome calculator, a key equation solver, a Chien search and an error value evaluator. The 4.22×64 mm2 chip with a 2.90×2.88 mm2 core uses a cell library in a 0.6 μm SPDM CMOS process.",

author = "Hsie-Chia Chang and C. Shung",

year = "1998",

month = jan,

day = "1",

doi = "10.1109/ISSCC.1998.672548",

language = "English",

pages = "390--391, 470",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 05-02-1998 Through 07-02-1998",

}

TY - JOUR

T1 - Reed-Solomon product-code (RS-PC) decoder for DVD applications

AU - Chang, Hsie-Chia

AU - Shung, C.

PY - 1998/1/1

Y1 - 1998/1/1

N2 - A Reed-Solomon product-code (RS-PC) is used in digital versatile disk (DVD) for error correction to mitigate the errors introduced during manufacturing or by user damage. The RS-PC decoder chip contains two frame buffer controllers that interface with two off-chip frame buffers, a row RS decoder and a column RS decoder. The parallel architecture minimizes the amount of frame buffer access and timing constraints on the RS decoders. Each RS decoder contains a syndrome calculator, a key equation solver, a Chien search and an error value evaluator. The 4.22×64 mm2 chip with a 2.90×2.88 mm2 core uses a cell library in a 0.6 μm SPDM CMOS process.

AB - A Reed-Solomon product-code (RS-PC) is used in digital versatile disk (DVD) for error correction to mitigate the errors introduced during manufacturing or by user damage. The RS-PC decoder chip contains two frame buffer controllers that interface with two off-chip frame buffers, a row RS decoder and a column RS decoder. The parallel architecture minimizes the amount of frame buffer access and timing constraints on the RS decoders. Each RS decoder contains a syndrome calculator, a key equation solver, a Chien search and an error value evaluator. The 4.22×64 mm2 chip with a 2.90×2.88 mm2 core uses a cell library in a 0.6 μm SPDM CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=0031652012&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.1998.672548

DO - 10.1109/ISSCC.1998.672548

M3 - Conference article

AN - SCOPUS:0031652012

SP - 390-391, 470

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

Y2 - 5 February 1998 through 7 February 1998

ER -