A new algebra called the redundant algebra is proposed and analyzed for the design of the ternary logic systems. The ternary systems can be realized by the dynamic CMOS logic circuits which are simple and fully compatible with that of the conventional binary logic circuits in process, power supply, and logic levels. A new dynamic differential logic called the CMOS Redundant Differential Logic (CRDL) is also developed to increase the logic flexibility and the circuit performance. The multiplier with redundant binary addition (RBA) tree is designed in both synchronous and pipelined systems. The synchronous RBAs designed by using the CRDL circuits shows a better speed performance than other proposed static RBAs. The pipelined multiplier designed by using the True-Single-Phase-Clock (TSPC) scheme has the advantageous features of higher operating frequency and less pipelined stages as compared to the conventional binary parallel pipelined multiplier. The experimental chip has been fabricated and measured which successfully verifies the correctness of the logic functions and the advantage in speed performance of the designed circuits.