Reducing timing discrepancy for energy-efficient on-chip memory architectures at low-voltage mode

Po Hao Wang, Tien-Fu Chen*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingChapter

Original languageEnglish
Title of host publicationSmart Sensors at the IoT Frontier
PublisherSpringer International Publishing
Pages73-106
Number of pages34
ISBN (Electronic)9783319553450
ISBN (Print)9783319553443
DOIs
StatePublished - 29 May 2017

Cite this

Wang, P. H., & Chen, T-F. (2017). Reducing timing discrepancy for energy-efficient on-chip memory architectures at low-voltage mode. In Smart Sensors at the IoT Frontier (pp. 73-106). Springer International Publishing. https://doi.org/10.1007/978-3-319-55345-0_4