Reducing memory latency via non-blocking and prefetching caches

Tien-Fu Chen*, Jean Loup Baer

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

82 Scopus citations

Abstract

Non-blocking caches and prefetching caches are two techniques for hiding memory latency by exploiting the overlap of processor computations with data accesses. A non-blocking cache allows execution to proceed concurrently with cache misses as long as dependency constraints are observed, thus exploiting post-miss operations. A prefetching cache generates prefetch requests to bring data in the cache before it is actually needed thus allowing overlap with premiss computations. In this paper, we evaluate the effectiveness of these two hardware-based schemes. We propose a hybrid design based on the combination of these approaches. We also consider compiler-based optimizations to enhance the effectiveness of non-blocking caches. Results from instruction level simulations on the SPEC benchmarks show that the hardware prefetching caches generally outperform non-blocking caches. Also, the relative effectiveness of non-blocking caches is more adversely affected by an increase in memory latency than that of prefetching caches. However, the performance of non-blocking caches can be improved substantially by compiler optimizations such as instruction scheduling and register renaming. The hybrid design can be very effective in reducing the memory latency penalty for many applications.

Original languageEnglish
Title of host publicationInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
PublisherPubl by ACM
Pages51-61
Number of pages11
Edition9
ISBN (Print)0897915356, 9780897915359
DOIs
StatePublished - 1 Jan 1992
EventProceedings of the Fifth International Conference on Architectural Support Programming Languages and Operating Systems - ASPLOS-V - Boston, MA, USA
Duration: 12 Oct 199215 Oct 1992

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
Number9
Volume27

Conference

ConferenceProceedings of the Fifth International Conference on Architectural Support Programming Languages and Operating Systems - ASPLOS-V
CityBoston, MA, USA
Period12/10/9215/10/92

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    Chen, T-F., & Baer, J. L. (1992). Reducing memory latency via non-blocking and prefetching caches. In International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS (9 ed., pp. 51-61). (International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS; Vol. 27, No. 9). Publ by ACM. https://doi.org/10.1145/143371.143486