Reducing AC power consumption by three-dimensional integration of Ge-on-insulator CMOS on 1-poly-6-metal 0.18 μm Si MOSFETs

D. S. Yu*, C. C. Liao, C. C. Chen, C. F. Lee, C. F. Cheng, Albert Chin, S. P. McAlister

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

We have used three-dimensional (3D) integration to reduce the ac power consumption in interconnects, which is the most severe issue beyond the dc power arising from the gate dielectric leakage current. From a direct calculation of the ac power consumption using an electromagnetic method, we show that both the ac power consumption and maximum operation frequency can be improved by integrating an additional integrated circuit layer. The 3D integration was realized by Ge-on-insulator (GOI) complementary metal oxide semiconductor field effect transistors (CMOSFETs) on 1-poly-6-metal (1P6M) 0.18 μm Si devices, where little performance degradation was measured in the lower layer 0.18 μm Si MOSFETs, due to the inherent low thermal budget (500°C rapid thermal anneal) of the GOI processing. The drive current of the 3D GOI n- and p-MOSFETs was more than double that of the control Si devices, providing another advantage of the approach.

Original languageEnglish
JournalJournal of the Electrochemical Society
Volume152
Issue number8
DOIs
StatePublished - 7 Oct 2005

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