Reduce the memory bandwidth of 3D graphics hardware with a novel rasterizer

Cheng Hsien Chen*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Currently, memory bandwidth has become the main bottleneck in graphics system. Reducing the memory access can reduce the power consumption and boost overall system performance. Low power technique is more important for graphics applications on hand-held or mobile device. In this paper, we propose a novel visibility driven rasterizer to reduce the memory arrass and operations on invisible pixels. It integrates with two-level hierarchical Z-buffer to do visibility driven rasterization. The rasterization scheme is tile-order scan-line based, and the rasterizer can smartly change the tile-size depending on the triangle size. This technique can balance the rasterization loading under different triangles. Moreover, we propose a fast visibility test algorithm to quickly reject a group of pixels within the tile. Simulation results show that the overall bandwidth reduction can be up to 60% under our test images.

Original languageEnglish
Pages (from-to)377-391
Number of pages15
JournalJournal of Circuits, Systems and Computers
Issue number4
StatePublished - 1 Aug 2002


  • Graphics processor
  • Hierarchical Z-buffer
  • Rasterizer

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