Next-generation digital entertainment and mobile communication devices are anticipated to require greater processor performance. To meet these demands, several researchers have attached a reconfigurable hardware accelerator to the base processor core. The reconfigurable hardware accelerator, termed a reconfigurable customized functional unit (RCFU), is usually realized by multiple processing elements (PE) organized in matrix form. The structure of the RCFU is generated from hot operation patterns of specific applications. Other than the RCFU, 'multiple-issue' is another microarchitectural technique to increase the performance. However, the impact of combining both of these approaches in the same design is not yet well understood. This problem motivates us to design RCFU generation and exploitation algorithms for a multiple-issue processor. To allow more operations to execute on the RCFU simultaneously, the proposed generation algorithm merges several data-independent operation patterns to construct the RCFU architecture. To schedule operations on both the RCFU and functional units (FU) of the base processor core simultaneously, the proposed exploitation algorithm presents a model to represent all available computing resources from both the FUs of the base processor and the PEs in the RCFU. Using this model, the RCFU exploitation problem can be considered as an instruction-scheduling problem. Our experiment achieves an average improvement in execution performance of 50% compared with previous efforts [2, 5].
- Application-specific processor (ASP)
- Customizable processor
- Extended instruction (EI)
- Reconfigurable customized functional unit (RCFU)