Recent research in clock power saving with multi-bit flip-flops

Po-Hung Lin*, Chih Cheng Hsu, Yao Tsung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

In modern large-scale, high-speed digital integrated circuit (IC) design, power consumption of the clock network usually dominates the dynamic power of the chip due to its highest switching rate. To effectively minimize the power consumption of the clock network, recent studies have been investigating the usage of multi-bit flip-flops (MBFFs). This paper presents the advantages of applying MBFFs, introduces various MBFF design flows, surveys key techniques for design optimization with MBFFs, and provides some future research directions in clock power saving with MBFFs.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
StatePublished - 13 Oct 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: 7 Aug 201110 Aug 2011

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period7/08/1110/08/11

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    Lin, P-H., Hsu, C. C., & Chang, Y. T. (2011). Recent research in clock power saving with multi-bit flip-flops. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026538] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026538