Recent research in analog placement considering thermal gradient

Po-Hung Lin*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

With the thermal effect, improper analog placements may degrade circuit performance because the thermal gradient can affect electrical characteristics of the thermally-sensitive devices. To mitigate the thermal effect in analog layout design, it is required to reduce thermally-induced mismatches among matched devices in addition to eliminating thermal hot spots. This paper presents major challenges for analog placement arising from the chip thermal gradient, introduces non-uniform and uniform thermal profiles as well as the corresponding placement configurations, surveys key existing techniques for analog placement under non-uniform and uniform thermal profiles, and provides the experimental results for analog placement with thermal consideration.

Original languageEnglish
Title of host publication2011 20th European Conference on Circuit Theory and Design, ECCTD 2011
Pages349-352
Number of pages4
DOIs
StatePublished - 7 Nov 2011
Event2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 - Linkoping, Sweden
Duration: 29 Aug 201131 Aug 2011

Publication series

Name2011 20th European Conference on Circuit Theory and Design, ECCTD 2011

Conference

Conference2011 20th European Conference on Circuit Theory and Design, ECCTD 2011
CountrySweden
CityLinkoping
Period29/08/1131/08/11

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