Recent advances of RTN technique towards the understanding of the gate dielectric reliability in trigate FinFETs

Steve S. Chung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The experimental RTN-trap profiling method bas been demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. The positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.

Original languageEnglish
Title of host publicationProceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages33-37
Number of pages5
ISBN (Electronic)9781467382588
DOIs
StatePublished - 9 Sep 2016
Event23rd IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016 - Singapore, Singapore
Duration: 18 Jul 201621 Jul 2016

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2016-September

Conference

Conference23rd IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2016
CountrySingapore
CitySingapore
Period18/07/1621/07/16

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