Recent advances in ASIC-compatible circuit techniques for a SOC in newly emerging application areas: Invited paper

Sang H. Dhong*, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We review advances in ASIC-compatible circuits for emerging SOC areas. These applications require ubiquitously low-power consumption during standby mode while providing a required performance in active mode. Sub- or near-threshold circuits may provide a low-power solution. However, they have yet to show how they fit into overall SOC optimization including area and performance. Selectively introducing custom-circuit techniques with ASIC tool compatibility have proven very attractive in reducing both the power and the area of a SOC by extending its Dynamic Voltage-Frequency Scaling (DVFS) range down to a VDD of 0.5 V.

Original languageEnglish
Title of host publicationISOCC 2014 - International SoC Design Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages24-25
Number of pages2
ISBN (Electronic)9781479951260
DOIs
StatePublished - 16 Apr 2015
Event11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of
Duration: 3 Nov 20146 Nov 2014

Publication series

NameISOCC 2014 - International SoC Design Conference

Conference

Conference11th International SoC Design Conference, ISOCC 2014
CountryKorea, Republic of
CityJeju
Period3/11/146/11/14

Keywords

  • 0.5V VDD
  • ASIC
  • DVFS
  • IOT
  • Pulse latch
  • SOC

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