Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS

Wen Shen Wuen*, Shen Fong Liu, Kuang Yu Chen, Kuei-Ann Wen

*Corresponding author for this work

Research output: Contribution to conferencePaper

2 Scopus citations

Abstract

The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with fT of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB.

Original languageEnglish
Pages460-463
Number of pages4
DOIs
StatePublished - 1 Dec 1999
Event1999 Asia Pacific Microwave Conference (APMC'99) 'Microwaves Enter the 21st Century' - Singapore, Singapore
Duration: 30 Nov 19993 Dec 1999

Conference

Conference1999 Asia Pacific Microwave Conference (APMC'99) 'Microwaves Enter the 21st Century'
CitySingapore, Singapore
Period30/11/993/12/99

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    Wuen, W. S., Liu, S. F., Chen, K. Y., & Wen, K-A. (1999). Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS. 460-463. Paper presented at 1999 Asia Pacific Microwave Conference (APMC'99) 'Microwaves Enter the 21st Century', Singapore, Singapore, . https://doi.org/10.1109/APMC.1999.829905