Realization of high-performance MOSFETs with gate lengths of 0.1 μm or less

Hisayo Sasaki Momose*, Mizuki Ono, Takashi Yoshitomi, Tatsuya Ohguro, Masanobu Saito, Hiroshi Iwai, Shin Ichi Nakamura

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


The reduction of gate length improves the performance of a MOSFET. However, this is difficult to do when the gate length is less than 0.1 μm for numerous reasons. This paper reports the results of improvement of the MOSFET performance employing various means. It was found that the current drive was only 30 percent higher with a gate length of 40 nm than with a gate length of 0.1 μm. Even when the gate oxide was 1.5 nm, which is half the oxide thickness for a direct tunneling leakage limit, it was found that the MOSFETs operate normally and the current drive was 1.6 times higher than when the gate oxide was 3 nm, because of the increase of gate capacitance. When a low-doped thin Si epitaxial layer was used as the intrinsic channel, the channel drive was improved by 20 percent because of higher carrier mobility, compared with the current-driving efficiency of a MOSFET formed by bulk material. The problem of source drain parasitic resistance increase in small-geometry MOSFETs was solved by using a novel device structure, i.e., S4D. Using this new structure, the parasitic resistance was reduced by one order of magnitude. Combining the aforementioned techniques, the current-driving efficiency could be improved further even when the gate length is in the sub-0.1 μm region.

Original languageEnglish
Pages (from-to)67-78
Number of pages12
JournalElectronics and Communications in Japan (Part II: Electronics)
Issue number10
StatePublished - Oct 1996


  • Downsizing
  • High performance

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