Realization of a systematic bit-wise decomposition metric

Chia Wei Chang*, Po-Ning Chen, Yunghsiang S. Han

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

Original languageEnglish
Pages1065-1068
Number of pages4
DOIs
StatePublished - 6 Dec 2004
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 6 Dec 20049 Dec 2004

Conference

Conference2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period6/12/049/12/04

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