Realistic worst-case SPICE file extraction using BSIM3

James C. Chen*, Chen-Ming Hu, Zhihong Liu, Ping K. Ko

*Corresponding author for this work

Research output: Contribution to journalConference article

10 Scopus citations

Abstract

In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these blocks will be determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gate implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance.

Original languageEnglish
Pages (from-to)375-378
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1 May 19954 May 1995

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