Evolution of electronic trap generation in the high-dielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.