Real-time observation of trap generation by scanning tunneling microscopy and the correlation to high-κ gate stack breakdown

Y. C. Ong, D. S. Ang, K. L. Pey, S. J. O'Shea, K. Kakushima, T. Kawanago, H. Iwai, C. H. Tung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Evolution of electronic trap generation in the high-dielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.

Original languageEnglish
Title of host publication2009 IEEE International Reliability Physics Symposium, IRPS 2009
Pages704-707
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE International Reliability Physics Symposium, IRPS 2009 - Montreal, QC, Canada
Duration: 26 Apr 200930 Apr 2009

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2009 IEEE International Reliability Physics Symposium, IRPS 2009
CountryCanada
CityMontreal, QC
Period26/04/0930/04/09

Keywords

  • Dielectric breakdown
  • High-κ
  • Scanning tunneling microscopy

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