Real-time high-definition stereo matching on FPGA

Lu Zhang*, Ke Zhang, Tian-Sheuan Chang, Gauthier Lafruit, Georgi Krasimirov Kuzmanov, Diederik Verkest

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

66 Scopus citations

Abstract

Although many fast stereo matching designs have been proposed in the past decades, it is still very challenging to achieve real-time speed at high definition resolution while maintaining high matching accuracy. In this paper, we propose a real-time high definition stereo matching design on FPGA. By using the Mini-Census transform and the Cross-based cost aggregation, the proposed algorithm is robust to radiometric differences and produces accurate disparity maps. The algorithm modules have been optimized for efficient hardware implementations and instantiated in an SoC environment. Implemented on a single EP3SL150 FPGA, our design achieves 60 frames per second for 1024 × 768 stereo images. Evaluated with the Middlebury stereo benchmark, the proposed design also delivers leading stereo matching accuracy among prior related work.

Original languageEnglish
Title of host publicationFPGA'11 - Proceedings of the 2011 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Pages55-64
Number of pages10
DOIs
StatePublished - 28 Mar 2011
Event2011 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'11 - Monterey, CA, United States
Duration: 27 Feb 20111 Mar 2011

Publication series

NameACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Conference

Conference2011 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'11
CountryUnited States
CityMonterey, CA
Period27/02/111/03/11

Keywords

  • FPGA
  • High-definition
  • Parallel computing
  • Stereo matching

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