Real-time computing of optical flow using adaptive VLSI neuroprocessors

Wai-Chi  Fang*, Bing J. Sheu, Ji Chien Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherPubl by IEEE
Pages122-125
Number of pages4
ISBN (Print)O81862079X
DOIs
StatePublished - 1 Sep 1990
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: 17 Sep 199019 Sep 1990

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Conference

ConferenceProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period17/09/9019/09/90

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