Random pulsewidth matching frequency synthesizer with sub-sampling charge pump

Te Wen Liao*, Chia Min Chen, Jun Ren Su, Chung-Chih Hung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This paper presents a fast locking phase-locked loop (FLPLL) system with reference-spur reduction techniques exploiting random pulsewidth matching and a sub-sampling charge pump. Through the randomization and average of the pulsewidth and the reduction of current mismatch, the frequency synthesizer can reduce the ripples on the control voltage of the voltage-controlled oscillator in order to reduce the reference spur at the output of the phase-locked loop. A random clock generator is used to perform a random selection control. The loop bandwidth of the system can be adjusted by the control voltage so as to reduce the locking time. To demonstrate the effectiveness of the proposed spur-reduction techniques, a 2.5 GHz to 2.7 GHz FLPLL was designed and fabricated using a TSMC 90-nm CMOS process. The proposed circuit can achieve a phase noise of-114 dBc/Hz at an offset frequency of 1 MHz and reference spurs below-74 dBc.

Original languageEnglish
Article number6265345
Pages (from-to)2815-2824
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number12
DOIs
StatePublished - 17 Aug 2012

Keywords

  • CMOS analog integrated circuits
  • frequency synthesizer
  • low spur
  • phase-locked loops (PLLs)
  • sub-sampling charge pump (SSCP)

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