Random-dopant-induced variability in nano-CMOS devices and digital circuits

Yiming Li*, Chih Hong Hwang, Tien Yeh Li

*Corresponding author for this work

Research output: Contribution to journalArticle

48 Scopus citations

Abstract

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of nand and nor circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of nand and nor are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.

Original languageEnglish
Pages (from-to)1588-1597
Number of pages10
JournalIEEE Transactions on Electron Devices
Volume56
Issue number8
DOIs
StatePublished - 2009

Keywords

  • Characteristic fluctuation
  • Modeling and simulation
  • Nanoscale digital IC
  • Random-dopant effect
  • Timing

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