Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS

Her-Ming Chiueh, Chia Hsiang Yang, Charles H.P. Wen, Chao Guang Yang, Po Hao Chien, Ching Yang Hung, Yu Jui Chen, Yao Pin Wang, Chin Fong Chiu, Jer Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18m CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET \lt 101.5 MeV-cm {2} / mg), validating the effectiveness of the methodology.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728160832
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
CountryTaiwan
CityHsinchu
Period10/08/2013/08/20

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