Quasi-planar NMOS FinFETs with sub-100nm gate lengths

N. Lindert*, Y. K. Choi, L. Chang, E. Anderson, W. Lee, T. J. King, J. Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

14 Scopus citations

Abstract

A simplified FinFET process having self-aligned double-gate advantage was developed. Device fabrication involved the development of silicon films from thermal oxidation of silion on insulator (SOI) wafers. The device was found to be insensitive to channel doping which showed the importance of the gate workfunction for scaling double gate devices.

Original languageEnglish
Pages26-27
Number of pages2
StatePublished - 1 Jan 2001
EventDevice Research Conference (DRC) - Notre Dame, IN, United States
Duration: 25 Jun 200127 Jun 2001

Conference

ConferenceDevice Research Conference (DRC)
CountryUnited States
CityNotre Dame, IN
Period25/06/0127/06/01

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