The source/drain quasi-planar FinFET devices were presented by the combination of the new FinFET process flow with a selective Ge growth technique. The current was raised by 28% with a Ge raised sorce/drain process in the double-gate devices. A minimal 3% degradation in drive current was produced as shown by the worst case misalignment. The current-voltage characteristics were measured and the absence of excessive gate current indicated that bridging between the gate and source/drain did not occur.
|Number of pages||2|
|State||Published - 1 Jan 2001|
|Event||2001 IEEE International SOI Conference - Durango, CO, United States|
Duration: 1 Oct 2001 → 4 Oct 2001
|Conference||2001 IEEE International SOI Conference|
|Period||1/10/01 → 4/10/01|