QAM/VSB dual mode equalizer design and implementation

C. F. Wu, M. T. Shiue, C. C. Huang, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A novel architecture for dual mode equalizer of CATV modem is proposed. It is not only suitable for quadrature amplitude modulation (QAM) system but also suitable for vestigial sideband modulation (VSB) system. This dual mode equalizer consists of fractionally spaced equalizer (FSE) and decision feedback equalizer (DFE) architecture. The FSE has 12 taps filter and uses sign-delayed LMS (SDLMS) coefficients updating methodology with "stop-and-go" algorithm. The DFE has 13 taps filter and uses sign-delayed LMS coefficients updating methodology. Also, a multi-state control scheme, a multi-slice slicer and a multi-step size are used to speed up the convergence of system. The system data rate is 5 MBaud and the maximum internal operation clock of the equalizer is 102 MHz. The chip is implemented with 0.6 μm CMOS TSMC 1P3M technology. The core area is 4044 μm×4044 μm and consumes 1.938 W power consumption.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages323-326
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
StatePublished - 1 Jan 1999
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 23 Aug 199925 Aug 1999

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
CountryKorea, Republic of
CitySeoul
Period23/08/9925/08/99

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