A novel architecture for dual mode equalizer of CATV modem is proposed. It is not only suitable for quadrature amplitude modulation (QAM) system but also suitable for vestigial sideband modulation (VSB) system. This dual mode equalizer consists of fractionally spaced equalizer (FSE) and decision feedback equalizer (DFE) architecture. The FSE has 12 taps filter and uses sign-delayed LMS (SDLMS) coefficients updating methodology with "stop-and-go" algorithm. The DFE has 13 taps filter and uses sign-delayed LMS coefficients updating methodology. Also, a multi-state control scheme, a multi-slice slicer and a multi-step size are used to speed up the convergence of system. The system data rate is 5 MBaud and the maximum internal operation clock of the equalizer is 102 MHz. The chip is implemented with 0.6 μm CMOS TSMC 1P3M technology. The core area is 4044 μm×4044 μm and consumes 1.938 W power consumption.