In this paper, a PVT Insensitive Time to Digital Converter is proposed to provide a stable reference clock signal of a phase-locked loop. The time resolution can be independent on process, voltage, and temperature variations. In order to produce 16-phase signals, eight series of differential delay elements are utilized. Then, interpolated architecture is used to increase the reference frequency such that the time resolution of the time digital converter is improved. Furthermore, implementing a delay element in the oscillator and replica bias circuit can enhance the linearity of the KVCO. Finally, this paper proposes the use of a symmetric time-Amplify control circuit, hence, the output pulse width and input cycle time can be synchronized. As the amplification increases the resolution increases, achieving the best resolution of 4.73ps and a maximum detection time of 57.2ns. The test chip is implemented with TSMC 0.18um 1P6M process. The chip area is 0.77×0.32mm2 and the power consumption is 120mW.