Pulse-width-modulation feedforward neural network design with on-chip learning

Jenn Chyou Bor*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under ±0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.

Original languageEnglish
Pages369-372
Number of pages4
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
Duration: 18 Nov 199621 Nov 1996

Conference

ConferenceProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
CitySeoul, South Korea
Period18/11/9621/11/96

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