In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under ±0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.
|Number of pages||4|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea|
Duration: 18 Nov 1996 → 21 Nov 1996
|Conference||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems|
|City||Seoul, South Korea|
|Period||18/11/96 → 21/11/96|