The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with SRCMOS test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. An experimental 64-bit latch array and self-timed control macro, designed for 2.5 V 0.5 μm CMOS technology, has been successfully fabricated and tested. The full circuit occupies an area of 1.704 mm×0.07 mm, and the size of latch bit cell is 21.6 μm×70 μm. Experimental results have shown the conversion latch to function properly, capturing 1.2 ns output pulses from an SRCMOS register file, and properly converting them to static levels. The measured delay from global clock to static output was 725 ps.
|Number of pages||6|
|State||Published - 1 Dec 1997|
|Event||Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA|
Duration: 12 Oct 1997 → 15 Oct 1997
|Conference||Proceedings of the 1997 International Conference on Computer Design|
|City||Austin, TX, USA|
|Period||12/10/97 → 15/10/97|