Prototype IC with WDDL and differential routing - DPA resistance assessment

Kris Tiri*, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

*Corresponding author for this work

Research output: Contribution to journalConference article

96 Scopus citations

Abstract

Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

Original languageEnglish
Pages (from-to)354-365
Number of pages12
JournalLecture Notes in Computer Science
Volume3659
DOIs
StatePublished - 4 Nov 2005
Event7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005 - Edinburgh, United Kingdom
Duration: 29 Aug 20051 Sep 2005

Keywords

  • Countermeasure
  • Differential power analysis (DPA)
  • Differential routing
  • Dual rail with precharge
  • Parasitic capacitance matching
  • Side-channel attack (SCA)
  • Wave dynamic differential logic (WDDL)

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    Tiri, K., Hwang, D., Hodjat, A., Lai, B-C., Yang, S., Schaumont, P., & Verbauwhede, I. (2005). Prototype IC with WDDL and differential routing - DPA resistance assessment. Lecture Notes in Computer Science, 3659, 354-365. https://doi.org/10.1007/11545262_26