Prospects for low-power, high-speed MPUs using 1.5nm direct-tunneling gate oxide MOSFETs

Hisayo Sasaki Momose*, Mizuki Ono, Takashi Yoshitomi, Tatsuya Ohguro, Shin Ichi Nakamura, Masanobu Saito, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

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