Programmable FIR filter with adder-based computing engine

Yu Ting Kuo; Tay Jyi Lin; Yi Cho; Chih-Wei Liu; Chein Wei Jen

doi:10.1109/ISCAS.2006.1692945

Programmable FIR filter with adder-based computing engine

Yu Ting Kuo^*, Tay Jyi Lin, Yi Cho, Chih-Wei Liu, Chein Wei Jen

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13μm implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%-18% computing time of MAC-based FIR cores with comparable filtering performance.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	1756-1759
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1692945
State	Published - 1 Dec 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country	Greece
City	Kos
Period	21/05/06 → 24/05/06

Access to Document

10.1109/ISCAS.2006.1692945

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Cite this

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title = "Programmable FIR filter with adder-based computing engine",

abstract = "This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13μm implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%-18% computing time of MAC-based FIR cores with comparable filtering performance.",

author = "Kuo, {Yu Ting} and Lin, {Tay Jyi} and Yi Cho and Chih-Wei Liu and Jen, {Chein Wei}",

year = "2006",

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Kuo, YT, Lin, TJ, Cho, Y, Liu, C-W & Jen, CW 2006, Programmable FIR filter with adder-based computing engine. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1692945, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1756-1759, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06. https://doi.org/10.1109/ISCAS.2006.1692945

Programmable FIR filter with adder-based computing engine. / Kuo, Yu Ting; Lin, Tay Jyi; Cho, Yi; Liu, Chih-Wei; Jen, Chein Wei.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 1756-1759 1692945 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Jen, Chein Wei

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N2 - This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13μm implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%-18% computing time of MAC-based FIR cores with comparable filtering performance.

AB - This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13μm implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%-18% computing time of MAC-based FIR cores with comparable filtering performance.

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