Programmable FIR filter with adder-based computing engine

Yu Ting Kuo*, Tay Jyi Lin, Yi Cho, Chih-Wei Liu, Chein Wei Jen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13μm implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%-18% computing time of MAC-based FIR cores with comparable filtering performance.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages1756-1759
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period21/05/0624/05/06

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