Abstract
In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.
Original language | English |
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Title of host publication | Silicon Nanoelectronics Workshop (SNW) |
Pages | 101-102 |
Number of pages | 2 |
DOIs | |
State | Published - 2017 |