Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory

Chia Chi Fan; Yu Chien Chiu; Chien Liu; Guan Lin Liou; Wen-Wei Lai; Yi Ru Chen; Tun-Jen Chang; Wan-Hsin Chen; Chun-Hu Cheng; Chun-Yen Chang

doi:10.23919/SNW.2017.8242317

Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory

Chia Chi Fan, Yu Chien Chiu, Chien Liu, Guan Lin Liou, Wen-Wei Lai, Yi Ru Chen, Tun-Jen Chang, Wan-Hsin Chen, Chun-Hu Cheng, Chun-Yen Chang

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

Original language	English
Title of host publication	Silicon Nanoelectronics Workshop (SNW)
Pages	101-102
Number of pages	2
DOIs	https://doi.org/10.23919/SNW.2017.8242317
State	Published - 2017

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@inproceedings{f35e783ab60b428aa5f0c7c0f60d2ee3,

title = "Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory",

abstract = "In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.",

author = "Fan, {Chia Chi} and Chiu, {Yu Chien} and Chien Liu and Liou, {Guan Lin} and Wen-Wei Lai and Chen, {Yi Ru} and Tun-Jen Chang and Wan-Hsin Chen and Chun-Hu Cheng and Chun-Yen Chang",

year = "2017",

doi = "10.23919/SNW.2017.8242317",

language = "English",

pages = "101--102",

booktitle = "Silicon Nanoelectronics Workshop (SNW)",

}

Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory. / Fan, Chia Chi; Chiu, Yu Chien; Liu, Chien; Liou, Guan Lin; Lai, Wen-Wei; Chen, Yi Ru; Chang, Tun-Jen; Chen, Wan-Hsin; Cheng, Chun-Hu; Chang, Chun-Yen.

Silicon Nanoelectronics Workshop (SNW). 2017. p. 101-102.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory

AU - Fan, Chia Chi

AU - Chiu, Yu Chien

AU - Liu, Chien

AU - Liou, Guan Lin

AU - Lai, Wen-Wei

AU - Chen, Yi Ru

AU - Chang, Tun-Jen

AU - Chen, Wan-Hsin

AU - Cheng, Chun-Hu

AU - Chang, Chun-Yen

PY - 2017

Y1 - 2017

N2 - In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

AB - In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

U2 - 10.23919/SNW.2017.8242317

DO - 10.23919/SNW.2017.8242317

M3 - Conference contribution

SP - 101

EP - 102

BT - Silicon Nanoelectronics Workshop (SNW)

ER -