Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory

Chia Chi Fan, Yu Chien Chiu, Chien Liu, Guan Lin Liou, Wen-Wei Lai, Yi Ru Chen, Tun-Jen Chang, Wan-Hsin Chen, Chun-Hu Cheng, Chun-Yen Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.
Original languageEnglish
Title of host publication Silicon Nanoelectronics Workshop (SNW)
Pages101-102
Number of pages2
DOIs
StatePublished - 2017

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