We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 2003|
|Event||IEEE International Electron Devices Meeting - Washington, DC, United States|
Duration: 8 Dec 2003 → 10 Dec 2003