Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering

C. H. Ge*, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

103 Scopus citations


We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, suicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

Original languageEnglish
Pages (from-to)73-76
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 2003
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: 8 Dec 200310 Dec 2003

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