Process Roadmap and Challenges for Metal Barriers

P. Moon*, V. Dubin, S. Johnston, Jih-Perng Leu, K. Raol, C. Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

17 Scopus citations

Abstract

Copper interconnects require two types of barrier layers: a liner on the sides and bottoms of the damascene features and a cap on top of the damascene features. The key functions of the barrier layers are to prevent copper and oxygen diffusion and promote adhesion with both the interlayer dielectric (ILD) and the copper. The cap layer must also protect the copper from corrosion during subsequent patterning steps and act as an etchstop for partially landed vias. Most copper damascene processes use a PVD Ta and/or Ta(N) alloy liner and PECVD SiN or SiCN dielectric cap. However, as copper interconnects continue to scale to finer dimensions these metal barrier technologies become problematic due to wiring resistance and current density issues. This paper describes some of the alternative liner and cap technologies that are being developed to address these issues.

Original languageEnglish
Pages (from-to)841-844
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 2003
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: 8 Dec 200310 Dec 2003

Fingerprint Dive into the research topics of 'Process Roadmap and Challenges for Metal Barriers'. Together they form a unique fingerprint.

Cite this