Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

Carlos H. Diaz*, Mi Chang Chang, Tong Chern Ong, Jack Yuan Chen Sun

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.

Original languageEnglish
Pages (from-to)444-449
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume38
Issue number3
DOIs
StatePublished - Mar 2003

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