Problems and solutions for downsizing CMOS below 0.1 μm

Hiroshi Iwai*, Shun Ichiro Ohmi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Progress of MOS LSI has been achieved by continuous downsizing of its components. However, the downsizing of CMOS devices is now facing severe difficulties at 0.1μm generation because of various expected limitations. In order to overcome the problems, introduction of new materials and device structures are investigated. This paper explains the difficulties of downsizing CMOS devices below 0.1 μm, and then, future CMOS technologies for new materials, processes and structures which are expected to solve the problems.

Original languageEnglish
Title of host publicationICSE 2000 - 2000 IEEE International Conference on Semiconductor Electronics, Proceedings
Pages1-19
Number of pages19
StatePublished - 2000
Event2000 4th IEEE International Conference on Semiconductor Electronics, ICSE 2000 - Port Dickson, Malaysia
Duration: 13 Nov 200015 Nov 2000

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Conference

Conference2000 4th IEEE International Conference on Semiconductor Electronics, ICSE 2000
CountryMalaysia
CityPort Dickson
Period13/11/0015/11/00

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